(China (Mainland))
Product Summary
EPM3064ATC100-10N device is a low-cost, high-performance device based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM3064ATC100-10N device operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. EPM3064ATC100-10N device in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group.
Parametrics
EPM3064ATC100-10N absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -0.5 to 4.6 V; (2)VI DC input voltage: -2.0 to 5.75 V; (3)IOUT DC output current, per pin: -25 to 25 mA; (4)TSTG Storage temperature No bias: -65 to 150 ℃; (5)TA Ambient temperature Under bias: -65 to 135 ℃; (6)TJ Junction temperature PQFP and TQFP packages, under bias: 135 ℃.
Features
EPM3064ATC100-10N features: (1)High.performance, low.cost CMOS EEPROM.based programmable logic devices (PLDs) built on a MAXR architecture; (2)Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (3)High–density PLDs ranging from 600 to 10,000 usable gates; (4)4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz; (5)Hot–socketing support; (6)Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance; (7)PCI compatible; (8)Bus–friendly architecture including programmable slew–rate control; (9)Open–drain output option; (10)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (11)Programmable power–saving mode for a power reduction of over 50% in each macrocell; (12)Configurable expander product–term distribution, allowing up to 32 product terms per macrocell; (13)Programmable security bit for protection of proprietary designs.
Diagrams
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 EPM3064ATC100-10N |
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IC MAX 3000A CPLD 64 100-TQFP |
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