EPM3032ALC44-10N

Product Summary

The EPM3032ALC44-10N is a low-cost, high-performance device based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM3032ALC44-10N operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. EPM3032ALC44-10N in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group.

Parametrics

EPM3032ALC44-10N absolute maximum ratings: (1)VCC Supply voltage With respect to ground (2): -0.5 to 4.6 V; (2)VI DC input voltage: -2.0 to 5.75 V; (3)IOUT DC output current, per pin: -25 to 25 mA; (4)TSTG Storage temperature No bias: -65 to 150 ℃; (5)TA Ambient temperature Under bias: -65 to 135 ℃; (6)TJ Junction temperature PQFP and TQFP packages, under bias 135 ℃.

Features

EPM3032ALC44-10N features: (1)High.performance, low.cost CMOS EEPROM.based programmable logic devices (PLDs) built on a MAXR architecture; (2)3.3-V in-system programmability (ISP) through the built.in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability; (3). ISP circuitry compliant with IEEE Std. 1532; (4)Built.in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (5)Enhanced ISP features: Enhanced ISP algorithm for faster programming; ISP_Done bit to ensure complete programming; Pull-up resistor on I/O pins during in.system programming; (6)High.density PLDs ranging from 600 to 10,000 usable gates; (7)4.5.ns pin.to.pin logic delays with counter frequencies of up to 227.3 MHz; (8)MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0.V, 3.3.V, and 2.5.V logic levels; (9)Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J.lead chip carrier (PLCC), and FineLine BGATM packages; (10)Hot.socketing support; (11)Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance.

Diagrams